1. Field of the Invention
The invention relates in general to a level shifter and level shifting method thereof, and more particularly to a level shifter of a non-volatile memory, which can ensure a normal operation of word-line selection and de-selection, and level shifting method thereof.
2. Description of the Related Art
FIG. 1A illustrates a conventional level shifter used in an X-decoder of a non-volatile memory. The level shifter 100 includes P-type metal oxide semiconductor (PMOS) transistors P1˜P3 and N-type metal oxide semiconductor (NMOS) transistors N1˜N3. The transistors P3 and N3 are used for receiving an input voltage Vin (alternating between GND and Vcc, e.g. 2.5V) and the transistors P1 and N1 are respectively used for outputting the operational voltages Vp (e.g. 6V) and GND as an output voltage for selecting and de-selecting a word line WL.
When the input voltage Vin has the GND level, the transistors P3, N1 and N2 are turned off, and the transistor N3 is turned on to output the GND voltage. The transistor P1 is turned on by the GND voltage to output the operational voltage Vp as the output voltage for selecting the word line WL, and the transistor P2 is turned off by the output voltage.
When the input voltage Vin rises from the GND level to the Vcc level (e.g. 2.5V), the transistors N3, P1 and P2 are turned off, and the transistor P3 is turned on to lift up the source voltage Va toward Vcc. However, because the drain voltage Vb of the transistor N1 is still at the level Vp (e.g. 6V) immediately after the previous period, the transistor N2, controlled by the voltage Vb, will be partially turned on to lower down the source voltage Va of the transistor P3 toward GND, causing a fighting path between the turned-on transistors P3 and N2. As a result, the transistor N1, controlled by the source voltage Va of the transistor P3, is partially turned on to lower down the output voltage to only a level Vx between GND and Vp first instead of quickly dropping the output voltage to the GND level, as shown in FIG. 1B, thereby causing a failure of de-selecting the word line WL. Similarly, when the input voltage Vin drops from the Vcc level to the GND level in the following period, the output voltage will not quickly rise up to the voltage Vp level due to the fighting path between the turned-on transistors N3 and P2, also causing a failure of word-line selection.
One method for resolving the above issue is to adjust the source voltage Va of the transistor P3 (or the drain voltage Vd of the transistor N3) to approach the Vcc level so as to completely turn on the transistor N1 (or the transistor P1) to output the GND voltage (or Vp) in the de-selection (or selection) operation by increasing the resistance of the transistor N2 (or P2). However, increasing the resistance of the transistor N2 (or P2) will inevitably increase the length of the transistor N2 (or P2). Owing that there are normally 8,000 to 16,000 level shifters 100 used for selecting and de-selecting word lines WL in the non-volatile memory, even a small length increase of the transistor N2 (or P2) in the level shifter 100 will cause a great enlargement in the size of the X-decoder, which goes against the design tendency of the non-volatile memory to be thin and small.
Another prior art will lower the voltage of Vp in FIG. 1A from the high voltage, e.g. 6V to the Vcc level, e.g. 2.5V, and then perform pre-decoding switching. After the switching, the voltage Vp is raised from Vcc to the high voltage 6V. Although the scheme can avoid the above select/de-select problems, however, it will suffer from read speed loss.